1. Field of the Invention
The present invention generally relates to semiconductor technology and device designs, and more particularly to an organic-based thin film transistor device and a method for producing the same.
2. Description of the Related Art
Thin film transistors (TFTS) with active organic layers and polymer-based electronic components are emerging as an inexpensive alternative to silicon-based TFTs for some applications. The use of organic and polymeric materials provides two main advantages. First, organic-based devices can be produced using a simpler and cheaper fabrication process, in contrast to the expensive equipment and processing associated with silicon processing. Second, it is possible to fabricate the devices on flexible plastic substrates, due to the ability to process organic materials at lower temperatures, and to the greater mechanical flexibility of organic-based components relative to inorganic materials such as silicon and conductive metals. However, despite considerable research and development effort, organic-based TFTs have not yet reached commercialization, at least in part due to relatively poor device characteristics of prior art organic TFTs.
Fabrication of an all-organic TFT requires various organic or organic/inorganic hybrid materials: semiconductors, insulators, and conductors. The conductor may be selected from conducting polymers such as polyaniline and poly(ethylene dioxide thiophene), and metal or graphite colloid particle-based inks. There are a variety of polymeric organic insulators that may be used, such as polyamide or PMMA for the semiconductor. Organic p-type (hole transporting) and n-type (electron transporting) materials are both known in the art and have been tested as the semiconductive channel in TFTs.
In general, circuitry using organic transistors have the potential of reduced power consumption and simplicity in the design. However, complementary circuitry using both organic N and P channels transistors are not common, for example, U.S. Pat. No. 5,625,199, the complete disclosure of which is herein incorporated by reference, teaches a technique to fabricate complementary circuits with inorganic n-channel and organic p-channel thin film transistors. Additionally, U.S. Pat. No. 5,936,259, the complete disclosure of which is herein incorporated by reference, describes a switch based on a thin film transistor design (TFT) using a fused ring organic compound as semiconductor. Furthermore, U.S. Pat. No. 5,804,836, the complete disclosure of which is herein incorporated by reference, describes an image processor design which operates on an array of polymer grid triodes. Similarly, prior art disclosures also teach a 5-stage ring oscillator using copper hexadecafluorophthalocyanide as the n-channel material and oligothiophenel oligothiophene derivative as the p-channel material.
Two popular structures of an existing polymer thin-film transistor are shown in FIGS. 9(a) and 9(b). These structures have two major disadvantages. First, there is a comer thinning problem due to topography, and second, the most sensitive portion of the body element is exposed to process induced contamination. The resulting devices have poor performance and inconsistent properties. Shown in FIG. 9(a) is the first typical structure of the polymer transistor. The source 11 and drain 12 are first patterned. Then the body material 13 is deposited and patterned. The body 13 is a semiconductive polymer or oligomer, and it is applied to the surface of the source 11 and drain 12 islands by evaporation, spin-coating, dip-coating or printing, depending on the organic semiconductor used.
The body material 13 is patterned in one of three ways. The most common method is by evaporation of the semiconductive material through a shadow mask. The other two methods are printing (i.e., screen printing or inkjet printing) and using conventional lithography by first applying a protective coating over the semiconductor, then applying the photoresist, patterning, and etching. A brief thermal anneal may be needed, depending on which type of organic semiconductor material is used. The last step is applying a protective coating to the semiconductor to passivate the devices from contamination.
After patterning the body portion 13, the substrate is wet cleaned. The body surface, especially in the channel region, deteriorates due to the unwanted chemical reaction. After a thermal treatment, the body element 13 becomes thin around the comers 16, 17 of the source 11 and drain 12 due to reflow. Typically, semiconductors decompose before melting. The source/drain 11, 12 to body contact area are significantly reduced as the result of the comer thinning 16, 17 of the body element 13. Then, the gate material 14 is deposited after a thin insulating polymer 15 is coated on top of the body element 13 and the exposed source 11 and drain 12 regions.
Another common structure of the polymer TFT structure is shown in FIG. 9(b). The gate 14 is formed first, then an insulating polymer 15 is coated thereon. Again, the corner thinning problem presented at the corners 16, 17 of the gate 14 causes the possibility of shorting of source 11 and drain 12 to the gate 14. After the source 11 and drain 12 are formed, the body element 13 is formed. In this case, since the body to channel interface is not exposed to any chemical, the resulting transistor yield and performance is better than those of the first transistor.
In both of the bottom-contact devices shown in FIGS. 9(a) and 9(b), there is a well-documented problem with ensuring good contact between the electrodes and the organic semiconductor. One approach used to solve this problem has been to modify the surface properties of gold electrodes using thin self-assembled monolayers, which improves wetting of the electrode by the organic semiconductor and may also decrease the chance of delaminating. However, the topography of the bottom electrodes may still hamper film formation and reduce the contact area. Therefore, there is a need for a new and improved structure and method for forming a polymer thin film transistor, which does not have the problems inherent with the prior art devices.
In view of the foregoing and other problems, disadvantages, and drawbacks of the conventional thin film transistor devices, the present invention has been devised, and it is an object of the present invention to provide a structure and method for a polymer thin film transistor with contact etch stops.
Another object of the present invention is to provide a thin film p olymer transistor having a vertical channel, or a transistor whose channel is structured in the third dimension (or 3-D). Yet another object of the present invention is to provide a new polymer thin film transistor structure and method which will result in a high-performance device. Still another object of the invention is to provide a polymer transistor structure so that its base layer is always protected from being contaminated during all process steps. It is yet another object of the invention to insure that the material thinning problem, inherent in conventional devices, is completely eliminated.
In order to attain the objects suggested above, there is provided, according to one aspect of the invention a vertical polymer transistor structure having a first conductive layer, filler structures co-planar with the first conductive layer, a semiconductor body layer above the first conductive layer, a second conductive layer above the semiconductor body layer, and an etch stop strip positioned between a portion of the first conductive layer and the semiconductor body layer. The vertical polymer transistor structure has filler structures that are electrically isolated from the first conductive layer. The filler structures are made of the same material as the first conductive layer. The first conductive layer, the semiconductor body layer, and the second conductive layer have laminated stacks of layers. The vertical polymer transistor structure has a source contact electrically connected to the first conductive layer and a drain contact electrically connected to the second conductive layer, the source contact is on an opposite side of the laminated stack from the drain contact. The filler structures support the source contact and the drain contact, and are positioned below the source contact and below the drain contact. The etch stop strip is positioned at an outer edge of the semiconductor body layer. Having an insulating sidewall spacer connected to the side of the second conductive layer and the semiconductor body layer, the etch stop strip is also between the sidewall spacer and the first conductive layer. The vertical polymer transistors structure has sidewall spacers on adjacent sides of the second conductive layer and the semiconductor body layer, the etch stop strip is also between only one sidewall spacer and the first conductive layer and on only one side of the vertical polymer of transistor structure.
A vertical polymer transistor structure is formed by depositing a first conductive layer on a substrate, patterning an etch stop strip over the first conductive layer, depositing a semiconductor body layer over the first conductive layer, and depositing a second conductive layer over the semiconductor body layer. The first conductive layer, the semiconductor body layer, and the second conductive layer have a laminated stack. Patterning the laminated stack creates a first laminated structure and filler structures adjacent the first laminated structure. Patterning the semiconductor body layer and the second conductor layer of the first laminated structure creates a second laminated structure. The etch stop strip protects the first conductive layer during the patterning of the first laminated structure. The invention removes at least a portion of the etch stop strip to expose the first conductive layer and forms contacts to the first conductive layer and the second conductive layer over the filler structures. The filler structures support the source contact and the drain contact. Before removing the etch stop strip, the invention forms sidewall spacers adjacent sides of the laminated structure and the etch stop strip protects the first conductive polymer layer during the forming of the sidewall spacers. The patterning of the etch stop strip positions the etch stop strip at an outer edge of the semiconductor body layer and on only one side of the vertical polymer of transistor structure. The source contact is on the opposite side of the laminated stack from the drain contact.
The features of the inventive vertical polymer thin-film transistor are several. For example, the device uses an etch-stop layer to control contact accuracy. Otherwise, over or under etch will cause a short or poor contact to the device, respectively. Next, the use of a dummy filler structure ensure planarization of the gate and contact material in order to prevent the material thinning problems (inherent in the prior art devices) due to thermal reflow over the sharp corner areas. Also, a high-k dielectric polymer is used to form the gate dielectric to boost the device performance. Another advantage is that the channel length of the device can be much shorter than those of the conventional planar devices. The channel length is defined by the thickness of the semiconductive polymer layer. The channel is limited only by the thinnest film which can tolerate film integrity challenges such as pin holes. Moreover, polymer spacers are used to prevent shorting between conductive polymer layers.